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MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator
The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew
Features http://onsemi.com MARKING DIAGRAM*
* * * * * * * *
450 ps Typical Propagation Delay Maximum Frequency > 1.5 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V PNP LVTTL Inputs for Minimal Loading Q Output Will Default HIGH with Inputs Open The 100 Series Contains Temperature Compensation. Pb-Free Packages are Available*
A WL YY WW LQFP-32 FA SUFFIX CASE 873A
MC100 EPT622 AWLYYWW 32 1 = Assembly Location = Wafer Lot = Year = Work Week
*For additional marking information, refer to Application Note AND8002/D.
Table 1. TRUTH TABLE
ENPECL H H X X L ENTTL X X H H L D H L H L X Q H L H L L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 4
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Publication Order Number: MC100EPT622/D
MC100EPT622
ENPECL VCCO VCCO VCCO Q0 Q1 Q2 Q3 Q4 ENTTL D0 Q0
24 VCCO D0 D1 VEE D2 D3 D4 VCCO 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VCCO Q5 Q6 VCC Q7 Q8 Q9 VCCO LVCMOS/TTL
D1
Q1
D2
Q2
MC100EPT622
13 12 11 10 9
D3
Q3
D4
Q4 LVPECL
D5
2
3
4
5
6
7
8 D6
Q5
Q6
D7
D8
D9
ENTTL
ENPECL
VEE
D5
D6
D7
Q7
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
D8
Q8
Figure 1. 32-Lead LQFP Pinout (Top View)
D9 Q9
Figure 2. Logic Symbol Table 1. PIN DESCRIPTION
Pin D0:9 Q0:9 ENTTL ENPECL VCC, VCCO VEE Function Data Input (TTL) Data Outputs (PECL) Enable Control (TTL) Enable Control (PECL) Positive Supply Ground
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MC100EPT622
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 2 kV > 150 V > 2 kV Level 2 UL 94 V-0 @ 0.125 in 596 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol VCC VI Iout TA Tstg qJA qJC Tsol Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Parameter Condition 1 VEE = 0 V VEE = 0 V Continuous Surge VI VCC Condition 2 Rating 5 5 to 0 50 100 -40 to +85 -65 to +150 80 55 12 to 17 265 Unit V V mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40C to 85C
Symbol IIH IIHH IIL VIK VIH VIL Characteristic Input HIGH Current Input HIGH Current MAX Input LOW Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN= 2.7 V VIN= VCC VIN= 0.5 V IIN= -18 mA -1.2 2.0 0.8 -0.9 Min Typ Max 25 100 -0.6 Unit mA mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC100EPT622
Table 5. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40C to 85C
Symbol IIH IIL VIH VIL Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Condition VIN= 2420 mV VIN= 1490 mV 2075 1490 Min Typ Max 150 200 2420 1675 Unit mA mA mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 1)
-40C Symbol IEE VOH VOL Characteristic Power Supply Current Input High Voltage (Note 2) Input Low Current (Note 2) Min 85 2155 1355 Typ 115 2280 1520 Max 145 2405 1700 Min 90 2155 1355 25C Typ 120 2280 1520 Max 155 2405 1700 Min 95 2155 1355 85C Typ 130 2280 1520 Max 155 2405 1700 Unit mA mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC-2.0 V.
Table 7. AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 3)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 3) Propagation Delay to Output (Figure 4, Note 4) D to Q ENPECL to Q ENTTL to Q Random Clock Jitter (RMS) (See Figure 3) Output Rise/Fall Times (20% - 80%) Duty Cycle Skew (Note 5) D to Q ENPECL to Q ENTTL to Q Channel 0-7 Channel 8-9 100 Min 1.0 Typ 1.5 Max Min 1.0 25C Typ 1.5 Max Min 1.0 85C Typ 1.5 Max Unit GHz ps
100 150 300
450 500 450 0.7 200
800 875 800 3.0 450
100 150 300
500 500 500 0.7
875 875 800 3.0 250
100 200 300
500 550 500 0.7
800 925 800 3.0 300
tJITTER tr / tf TSKEW
ps ps ps
100
200
100
200
120 200 120 100
375 775 400 275
120 200 120 100
375 775 400 275
120 200 120 100
375 775 400 275
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 4. 1.5 V to 50% point of the output. 5. Duty cycle skew |tPLH - tPHL| on the specific path.
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MC100EPT622
2400 2200 OUTPUT AMPLITUDE (mV) 2000 1800 1600 1400 1200 1000 0.5 RMS Jitter (ps) VCC = 3.3 V TA = 25C VOH (mV) VOL (mV) 10.0 9.0 8.0 6.0 5.0 4.0 3.0 2.0 1.0 1.0 1.5 2.0 0.0 RMS JITTER (ps) 7.0
FREQUENCY (GHz)
Figure 3. Average Output Amplitude/Jitter (3.3 V, 255C)
800 700 600 tPLH, tPHL (ps) 500 400 300 200 100 0 tPLH tPHL
Figure 4. Average Propagation Delay (3.3 V, 255C)
Q Driver Device Q
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EE
CHANNEL Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V
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MC100EPT622
ORDERING INFORMATION
Device MC100EPT622FA MC100EPT622FAG MC100EPT622FAR2 MC100EPT622FAR2G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EPT622
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V V1
AE P AE
17
DETAIL Y
BASE METAL
N 9 -Z- S
8X M_
S1
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_
GAUGE PLANE
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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MC100EPT622/D
0.20 (0.008)
0.20 (0.008) AC T-U Z
F
EE EE EE
9
D
M
4X
AC T-U Z
DETAIL Y
-T-, -U-, -Z-

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